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| 1 mx29gl256f datasheet p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f
2 contents features ............................................................................................................................................................. 5 general features .................................................................................................................................. 5 performance ........................................................................................................................................... 5 software features ............................................................................................................................... 5 hardware features .............................................................................................................................. 5 pin configuration ........................................................................................................................................... 6 pin description ................................................................................................................................................. 7 block diagram .................................................................................................................................................. 8 block diagram description ........................................................................................................................ 9 block structure ........................................................................................................................................... 10 table 1. mx29gl256f sector architecture ................................................................................... 10 bus operation ................................................................................................................................................. 11 table 2-1. bus operation ....................................................................................................................... 11 table 2-2. bus operation ....................................................................................................................... 12 functional operation description ....................................................................................................... 13 read operation ..................................................................................................................................... 13 page read ................................................................................................................................................ 13 write operation ................................................................................................................................... 13 device reset .......................................................................................................................................... 13 standby mode ........................................................................................................................................ 13 output disable ...................................................................................................................................... 14 byte/word selection .......................................................................................................................... 14 hardware write protect ................................................................................................................. 14 accelerated programming operation ....................................................................................... 14 write buffer programming operation ....................................................................................... 14 sector protect operation .............................................................................................................. 15 automatic select bus operations ................................................................................................ 15 sector lock status verification .................................................................................................. 15 read silicon id manufacturer code ............................................................................................ 16 read indicator bit (q7) for security sector ............................................................................ 16 inherent data protection ................................................................................................................ 16 command completion ......................................................................................................................... 16 low vcc write inhibit .......................................................................................................................... 16 write pulse "glitch" protection ................................................................................................... 16 logical inhibit ........................................................................................................................................ 16 power-up sequence ............................................................................................................................ 17 power-up write inhibit ....................................................................................................................... 17 power supply decoupling ................................................................................................................ 17 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 3 command operations ................................................................................................................................... 18 reading the memory array .............................................................................................................. 18 automatic programming of the memory array ...................................................................... 18 erasing the memory array ............................................................................................................... 19 sector erase ......................................................................................................................................... 19 chip erase .............................................................................................................................................. 20 erase suspend/resume ...................................................................................................................... 21 sector erase resume ........................................................................................................................ 21 program suspend/resume ............................................................................................................... 22 program resume .................................................................................................................................. 22 buffer write abort ............................................................................................................................. 22 automatic select operations ......................................................................................................... 23 automatic select command sequence ........................................................................................ 23 read manufacturer id or device id .............................................................................................. 24 reset ........................................................................................................................................................ 24 advanced sector protection/un-protection .......................................................................... 25 figure 1. advance sector protection/unprotection spb program algorithm ............................................... 25 figure 2. lock register program algorithm ................................................................................................. 26 figure 3. spb program algorithm ................................................................................................................ 28 security sector flash memory region ...................................................................................... 31 table 3. command definitions .......................................................................................................... 32 common flash memory interface (cfi) mode ..................................................................................... 35 query command and command flash memory interface (cfi) mode ................................ 35 table 4-1. cfi mode: identifcation data values (note 1) ................................................................................ 35 table 4-2. cfi mode: system interface data values ................................................................................... 35 table 4-3. cfi mode: device geometry data values .................................................................................. 36 table 4-4. cfi mode: primary vendor-specifc extended query data values ............................................ 37 electrical characteristics .................................................................................................................... 38 absolute maximum stress ratings ............................................................................................... 38 operating temperature and voltage .......................................................................................... 38 maximum negative overshoot waveform ................................................................................................... 38 maximum positive overshoot waveform ..................................................................................................... 38 dc characteristics ............................................................................................................................. 39 switching test circuits .................................................................................................................... 40 test condition ............................................................................................................................................. 40 switching test waveforms ............................................................................................................. 40 ac characteristics ............................................................................................................................. 41 write command operation ......................................................................................................................... 43 figure 4. command write operation ................................................................................................ 43 read/reset operation ................................................................................................................................. 44 figure 5. read timing waveforms ...................................................................................................... 44 figure 6. reset# timing waveform ................................................................................................... 45 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 4 erase/program operation ........................................................................................................................ 46 figure 7. automatic chip erase timing waveform ....................................................................... 46 figure 8. automatic chip erase algorithm flowchart ............................................................ 47 figure 9. automatic sector erase timing waveform ................................................................ 48 figure 10. automatic sector erase algorithm flowchart .................................................... 49 figure 11. erase suspend/resume flowchart ............................................................................. 50 figure 12. automatic program timing waveforms ...................................................................... 51 figure 13. accelerated program timing diagram ....................................................................... 51 figure 14. ce# controlled write timing waveform ................................................................... 52 figure 15. automatic programming algorithm flowchart .................................................... 53 figure 16. silicon id read timing waveform .................................................................................. 54 write operation status .............................................................................................................................. 55 figure 17. data# polling timing waveforms (during automatic algorithms) .................. 55 figure 18. status polling for word program/erase ................................................................ 56 figure 19. status polling for write buffer program ............................................................. 57 figure 20. toggle bit timing waveforms (during automatic algorithms) ........................ 58 figure 21. toggle bit algorithm ........................................................................................................ 59 figure 22. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ................................................................................................................................................. 60 figure 23. page read timing waveform ............................................................................................ 61 figure 24. deep power down mode waveform ............................................................................ 62 figure 25. write buffer program flowchart ............................................................................. 63 recommended operating conditions .................................................................................................... 64 at device power-up .................................................................................................................................... 64 erase and programming performance ............................................................................................... 65 data retention ............................................................................................................................................... 65 latch-up characteristics ......................................................................................................................... 65 pin capacitance .............................................................................................................................................. 65 ordering information ................................................................................................................................. 66 part name description ................................................................................................................................ 67 package information ................................................................................................................................... 68 revision history ............................................................................................................................................ 71 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 5 features general features ? power supply operation - 2.7 to 3.6 volt for read, erase, and program operations - mx29gl256f h/l: vi/o=vcc=2.7v~3.6v , vi/o voltage must tight with vcc - mx29gl256f u/d: vi/o=1.65v~3.6v for input/output ? byte/w ord mode switchable - 33,554,432 x 8 / 16,777,216 x 16 ? 64kw/128kb uniform sector architecture - 256 equal sectors ? 16-byte/8-word page read buf fer ? 64-byte/32-word write buf fer ? extra 128-word sector for security - features factory locked and identifable, and customer lockable ? advanced sector protection function (solid and password protect) ? latch-up protected to 100ma from -1v to 1.5xvcc ? low vcc write inhibit : vcc vlko ? compatible with jedec standard - pinout and software compatible to single power supply flash ? deep power down mode performance ? high performance - fast access time: - mx29gl256f h/l: 100ns (vcc=2.7~3.6v), 90ns (vcc=3.0~3.6v) - mx29gl256f u/d: 1 10ns (vcc=2.7~3.6v, v i/o=1.65 to vcc) - page access time: - mx29gl256f h/l: 25ns - mx29gl256f u/d: 30ns - fast program time: 10us/word - fast erase time: 0.5s/sector ? low power consumption - low active read current: 10ma (typical) at 5mhz - low standby current: 20ua (typical) ? minimum 100,000 erase/program cycle ? 20 years data retention software features ? program/erase suspend & program/erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased - suspends sector program operation to read data from another sector which is not being program ? status reply - data# polling & toggle bits provide detection of program and erase operation completion ? support common flash interface (cfi) hardware features ? ready/busy# (r y/by#) output - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode ? wp#/acc input pin - hardware write protect pin/provides accelerated program capability package ? 56-pin tsop ? 56-ball fbga (7mm x 9mm) ? 64-ball lfbga (11mm x 13mm) ? all devices are rohs compliant and halogen-free single voltage 3v only flash memory p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 6 pin configuration 56 tsop 64 lfbga a b c d e f g h nc 8 7 6 5 4 3 2 1 a22 a23 vi/o nc nc nc a13 a12 a14 a15 a16 byte# q15/ a-1 a9 a8 a10 a11 q7 q14 q13 q6 we# a21 a19 res- et# q5 q12 vcc q4 wp#/ acc a18 a20 q2 q10 q11 ry/ by# a7 a17 a6 a5 q0 q8 q9 q1 q3 a3 a4 a2 a1 a0 ce# oe# gnd gnd gnd nc nc nc nc nc vi/o nc nc a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nc nc a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 v cc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 nc vi/o 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 7 pin description symbol pin name a0~a23 address input q0~q14 data inputs/outputs q15/a-1 q15(word mode)/lsb addr(byte mode) ce# chip enable input we# write enable input oe# output enable input reset# hardware reset pin, active low wp#/acc* hardware write protect/programming acceleration input ry/by# ready/busy output byte# selects 8 bits or 16 bits mode vcc +3.0v single power supply gnd device ground nc pin not connected internally vi/o power supply for input/output logic symbol 16 or 8 q0-q15 (a-1) ry/by# a0-a23 ce# oe# we# reset# wp#/acc byte# vi/o 24 notes: 1. wp#/acc has internal pull up. 2. for mx29gl256f h/l vi/o voltage must tight with vcc (vi/o = vcc =2.7v~3.6v). 56 fbga (7x9x1.2mm) a18 a17 q1 q9 q10 q2 a23 a20 q4 vi/o *1 we# a19 a9 a10 q6 q13 q12 q5 a8 reset# ry/by# q3 vcc q11 wp#/acc a12 a13 a14 nc q15 q7 q14 a11 a15 a21 a22 a16 nc nc gnd a6 a5 a4 gnd oe# q0 q8 a7 nc nc nc a3 a2 a1 a0 ce# 1 2 3 4 5 6 7 8 a b c d e f g h note: *1. g5 pin is nc on mx29gl256f h/l. *2. only support word mode for 56-fbga. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 8 block diagram control input logic program/erase high voltage write state machine (wsm) state register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 a0-am am: msb address ce# oe# we# reset# byte# wp#/acc p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 9 block diagram description the block diagram on page 8 illustrates a simplifed architecture of this device. each block in the block diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array. the "control input logic" block receives input pins ce#, oe#, we#, reset#, byte#, and wp#/acc. it creates internal timing control signals according to the input pins and outputs to the "address latch and buffer" to latch the external address pins a0-am(a23). the internal addresses are output from this block to the main array and decoders composed of "x-decoder", "y-decoder", "y-pass gate", and "flash ar - ray". the x-decoder decodes the word-lines of the fash array, while the y-decoder decodes the bit-lines of the fash array. the bit lines are electrically connected to the "sense amplifier" and "pgm data hv" se - lectively through the y-pass gates. sense amplifiers are used to read out the contents of the fash memo - ry, while the "pgm data hv" block is used to selectively deliver high power to bit-lines during programming. the "i/o buffer" controls the input and output on the q0-q15/a-1 pads. during read operation, the i/o buffer receives data from sense amplifiers and drives the output pads accordingly. in the last cycle of program command, the i/o buffer transmits the data on q0-q15/a-1 to "program data latch", which controls the high power drivers in "pgm data hv" to selectively program the bits in a word or byte according to the user in - put pattern. the "program/erase high voltage" block comprises the circuits to generate and deliver the necessary high voltage to the x-decoder, flash array, and "pgm data hv" blocks. the logic control module com - prises of the "write state machine, wsm", "state register", "command data decoder", and "command data latch". when the user issues a command by toggling we#, the command on q0-q15/a-1 is latched in the command data latch and is decoded by the command data decoder. the state register receives the command and records the current state of the device. the wsm implements the in - ternal algorithms for program or erase according to the current command state by controlling each block in the block diagram. array architecture the main fash memory array can be organized as byte mode (x8) or word mode (x16). the details of the ad - dress ranges and the corresponding sector addresses are shown in table 1. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 10 table 1. mx29gl256f sector architecture block structure sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa0 00000000 000000h-00ffffh 128 64 sa1 00000001 010000h-01ffffh 128 64 sa2 00000010 020000h-02ffffh 128 64 sa3 00000011 030000h-03ffffh : : : : : : : : : : : : : : : 128 64 sa252 11111100 fc0000h-fcffffh 128 64 sa253 11111101 fd0000h-fdffffh 128 64 sa254 11111110 fe0000h-feffffh 128 64 sa255 11111111 ff0000h-ffffffh p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 11 table 2-1. bus operation notes: 1. the frst or last sector was protected if wp#/acc=v il. 2. when wp#/acc = vih, the protection conditions of the outmost sector depends on previous protection condi - tions. refer to the advanced protect feature. 3. q0~q15 are input (din) or output (dout) pins according to the requests of command sequence, sector pro - tection, or data polling algorithm. 4. in w ord mode (byte#=vih), the addresses are am to a0, am: msb of address. in byte mode (byte#=v il), the addresses are am to a-1 (q15), am: msb of address. mode select re- set# ce# we# oe# address (note4) data i/o q7~q0 byte# wp#/ acc vil vih data (i/o) q15~q8 device reset l x x x x highz highz highz l/h standby mode vcc 0.3v vcc 0.3v x x x highz highz highz h output disable h l h h x highz highz highz l/h read mode h l h l ain dout q8-q14= highz, q15=a-1 dout l/h write h l l h ain din din note1,2 accelerate program h l l h ain din din vhv bus operation p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 12 notes: 1. sector unprotected code:00h. sector protected code:01h. 2. factory locked code: wp# protects high address sector: 99h. wp# protects low address sector: 89h factory unlocked code: wp# protects high address sector: 19h. wp# protects low address sector: 09h 3. am: msb of address. table 2-2. bus operation item control input am to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 q7 ~ q0 q15 ~ q8 ce# we# oe# sector lock status verifcation l h l sa x v hv x l x l h l 01h or 00h (note 1) x read silicon id manufacturer code l h l x x v hv x l x l l l c2h x read silicon id -- mx29gl256f cycle 1 l h l x x v hv x l x l l h 7eh 22h(word), xxh(byte) cycle 2 l h l x x v hv x l x h h l 22h 22h(word), xxh(byte) cycle 3 l h l x x v hv x l x h h h 01h 22h(word), xxh(byte) p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 13 functional operation description read operation to perform a read operation, the system addresses the desired memory array or status register location by pro - viding its address on the address pins and simultaneously enabling the chip by driving ce# & oe# low, and we# high. after the tce and toe timing requirements have been met, the system can read the contents of the addressed location by reading the data (i/o) pins. if either the ce# or oe# is held high, the outputs will remain tri-stated and no data will appear on the output pins. page read this device is able to conduct mxic maskrom compatible high performance page read. page size is 16 bytes or 8 words. the higher address amax ~ a3 select the certain page, while a2~a0 for word mode, a2~a-1 for byte mode select the particular word or byte in a page. the page access time is taa or tce, following by tpa for the rest of the page read time. when ce# toggles, access time is taa or tce. page mode can be turned on by keeping "page-read address" constant and changing the "intra-read page" addresses. write operation to perform a write operation, the system provides the desired address on the address pins, enables the chip by asserting ce# low, and disables the data (i/o) pins by holding oe# high. the system then places data to be written on the data (i/o) pins and pulses we# low. the device captures the address information on the falling edge of we# and the data on the rising edge of we#. to see an example, please refer to the timing diagram in figure 4 . the system is not allowed to write invalid commands (commands not defned in this datasheet) to the device. writing an invalid command may put the device in an undefned state. device reset driving the reset# pin low for a period of trp or more will return the device to read mode. if the device is in the middle of a program or erase operation, the reset operation will take at most a period of tready1 before the device returns to read mode. until the device does returns to read mode, the ry/by# pin will remain low (busy status). when the reset# pin is held at gnd0.3v, the device only consumes standby (isbr) current. however, the de - vice draws larger current if the reset# pin is held at a voltage greater than gnd+0.3v and less than or equal to vil. it is recommended to tie the system reset signal to the reset# pin of the fash memory. this allows the device to be reset with the system and puts it in a state where the system can immediately begin reading boot code from it. standby mode the device enters standby mode whenever the reset# and ce# pins are both held high except in the embed - ded mode. while in this mode, we# and oe# will be ignored, all data output pins will be in a high impedance state, and the device will draw minimal (isb) current. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 14 functional operation description (cont'd) output disable while in active mode (reset# high and ce# low), the oe# pin controls the state of the output pins. if oe# is held high, all data (i/o) pins will remain tri-stated. if held low, the byte or word data (i/o) pins will drive data. byte/word selection the byte# input pin is used to select the organization of the array data and how the data is input/output on the data (i/o) pins. if the byte# pin is held high, word mode will be selected and all 16 data lines (q0 to q15) will be active. if byte# is forced low, byte mode will be active and only data lines q0 to q7 will be active. data lines q8 to q14 will remain in a high impedance state and q15 becomes the a-1 address input pin. hardware write protect by driving the wp#/acc pin low. the highest or lowest was protected from all erase/program operations. if wp#/acc is held high (vih to vcc), these sectors revert to their previously protected/unprotected status. accelerated programming operation by applying high voltage (vhv) to the wp#/acc pin, the device will enter the accelerated programming mode. this mode permits the system to skip the normal command unlock sequences and program byte/word locations directly. during accelerated programming, the current drawn from the wp#/acc pin is no more than icp1. write buffer programming operation programs 64bytes/32words in a programming operation. to trigger the write buffer programming, start by the frst two unlock cycles, then third cycle writes the write buffer load command at the destined programming sec - tor address. the forth cycle writes the "word locations subtract one" number. following above operations, system starts to write the mingling of address and data. after the programming of the frst address or data, the "write-buffer-page" is selected. the following data should be within the above men - tioned page. the "write-buffer-page" is selected by choosing address amax-a5. "write-buffer-page" address has to be the same for all address/ data write into the write buffer. if not, operation will abort. to program the content of the write buffer page this command must be followed by a write to buffer program con - frm command. the operation of write-buffer can be suspended or resumed by the standard commands, once the write buffer programming operation is fnished, itll return to normal read mode. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 15 functional operation description (cont'd) write buffer programming operation (cont'd) abort will be executed for the write buffer programming sequence if following condition occurs: ? the value loaded is bigger than the page buffer size during "number of locations to program" ? address written in a sector is not the same as the one assigned during the write-buffer-load command. ? address/ data pair written to a different write-buffer-page than the one assigned by the "starting address" during the "write buffer data loading" operation. ? writing not "confrm command" after the assigned number of "data load" cycles. at write buffer abort mode, the status register will be q1=1, q7=data# (last address written), q6=toggle. a write-to-buffer-abort reset command sequence has to be written to reset the device for the next operation. write buffer programming can be conducted in any sequence. however the cfi functions, autoselect, secured silicon sector are not functional when program operation is in progress. multiple write buffer programming opera - tions on the same write buffer address range without intervening erases is available. any bit in a write buffer ad - dress range cant be programmed from 0 back to 1. sector protect operation the device provides user programmable protection operations for selected sectors. please refer to table 1 which show all sector assignments. during the protection operation, the sector address of any sector may be used to specify the sector being pro - tected. automatic select bus operations the following fve bus operations require a9 to be raised to vhv. please see automatic select command sequence in the command operations section for details of equivalent command operations that do not require the use of vhv. sector lock status verification to determine the protected state of any sector using bus operations, the system performs a read operation with a9 raised to vhv, the sector address applied to address pins a23 to a12, address pins a6, a3, a2 & a0 held low, and address pin a1 held high. if data bit q0 is low, the sector is not protected, and if q0 is high, the sector is protected. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 16 functional operation description (cont'd) read silicon id manufacturer code to determine the silicon id manufacturer code, the system performs a read operation with a9 raised to vhv and address pins a6, a3, a2, a1, & a0 held low. the macronix id code of c2h should be present on data bits q7 to q0. read indicator bit (q7) for security sector to determine if the security sector has been locked at the factory, the system performs a read operation with a9 raised to vhv, address pin a6, a3 & a2 held low, and address pins a1 & a0 held high. if the security sector has been locked at the factory, the code 99h(h)/89h(l) will be present on data bits q7 to q0. otherwise, the factory unlocked code of 19h(h)/09h(l) will be present. inherent data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read mode during power up. additionally, the following design features protect the device from unintended data corruption. command completion only after the successful completion of the specifed command sets will the device begin its erase or program operation. the failure in observing valid command sets will result in the memory returning to read mode. low vcc write inhibit the device refuses to accept any write command when vcc is less than vlko. this prevents data from spuriously being altered during power-up, power-down, or temporary power interruptions. the device automatically resets itself when vcc is lower than vlko and write commands are ignored until vcc is greater than vlko. the system must provide proper signals on control pins after vcc rises above vlko to avoid unintentional program or erase operations. write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# at vih, or oe# at vil. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 17 functional operation description (cont'd) power-up sequence upon power up, the device is placed in read mode. furthermore, program or erase operation will begin only after successful completion of specifed command sequences. power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 18 command operations reading the memory array read mode is the default state after power up or after a reset operation. to perform a read operation, please re - fer to read operation in the bus operations section above. if the device receives an erase suspend command while in the sector erase state, the erase operation will pause (after a time delay not exceeding 20us) and the device will enter erase-suspended read mode. while in the erase-suspended read mode, data can be programmed or read from any sector not being erased. reading from addresses within sector (s) being erased will only return the contents of the status register, which is in fact how the current status of the device can be determined. if a program command is issued to any inactive (not currently being erased) sector during erase-suspended read mode, the device will perform the program operation and automatically return to erase-suspended read mode after the program operation completes successfully. while in erase-suspended read mode, an erase resume command must be issued by the system to reactivate the erase operation. the erase operation will resume from where is was suspended and will continue until it completes successfully or another erase suspend command is received. after the memory device completes an embedded operation (automatic chip erase, sector erase, or program) successfully, it will automatically return to read mode and data can be read from any address in the array. if the embedded operation fails to complete, as indicated by status register bit q5 (exceeds time limit fag) going high during the operations, the system must perform a reset operation to return the device to read mode. there are several states that require a reset operation to return to read mode: 1. a program or erase failure--indicated by status register bit q5 going high during the operation. failures dur - ing either of these states will prevent the device from automatically returning to read mode. 2. the device is in auto select mode or cfi mode. these two states remain active until they are terminated by a reset operation. in the two situations above, if a reset operation (either hardware reset or software reset command) is not per - formed, the device will not return to read mode and the system will not be able to read array data. automatic programming of the memory array the device provides the user the ability to program the memory array in byte mode or word mode. as long as the users enters the correct cycle defned in the table 3 (including 2 unlock cycles and the a0h program com- mand), any byte or word data provided on the data lines by the system will automatically be programmed into the array at the specifed location. after the program command sequence has been executed, the internal write state machine (wsm) automatically executes the algorithms and timings necessary for programming and verifcation, which includes generating suit - able program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass verifcation or have low margins. the internal controller protects cells that do pass verifcation and mar - gin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells continue to be programmed. with the internal wsm automatically controlling the programming process, the user only needs to enter the pro - gram command and data once. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 19 command operations (cont'd) automatic programming of the memory array (cont'd) programming will only change the bit status from "1" to "0". it is not possible to change the bit status from "0" to "1" by programming. this can only be done by an erase operation. furthermore, the internal write verifcation only checks and detects errors in cases where a "1" is not successfully programmed to "0". any commands written to the device during programming will be ignored except hardware reset or program sus - pend. hardware reset will terminate the program operation after a period of time no more than 10us. when the embedded program algorithm is complete or the program operation is terminated by a hardware reset, the de - vice will return to read mode. program suspend ready, the device will enter program suspend read mode. after the embedded program operation has begun, the user can check for completion by reading the following bits in the status register: note: ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. erasing the memory array there are two types of erase operations performed on the memory array -- sector erase and chip erase. in the sector erase operation, one or more selected sectors may be erased simultaneously. in the chip erase operation, the complete memory array is erased except for any protected sectors. more details of the protected sectors are explained in section advanced sector protection/un-protection . sector erase the sector erase operation is used to clear data within a sector by returning all of its memory locations to the "1" state. it requires six command cycles to initiate the erase operation. the frst two cycles are "unlock cycles", the third is a confguration cycle, the fourth and ffth are also "unlock cycles", and the sixth cycle is the sector erase command. after the sector erase command sequence has been issued, an internal 50us time-out counter is started. until this counter reaches zero, additional sector addresses and sector erase commands may be is - sued thus allowing multiple sectors to be selected and erased simultaneously. after the 50us time-out counter has expired, no new commands will be accepted and the embedded sector erase operation will begin. note that the 50us timer-out counter is restarted after every erase command sequence. if the user enters any command other than sector erase or erase suspend during the time-out period, the erase operation will abort and the de - vice will return to read mode. after the embedded sector erase operation begins, all commands except erase suspend will be ignored. the only way to interrupt the operation is with an erase suspend command or with a hardware reset. the hardware reset will completely abort the operation and return the device to read mode. status q7 *1 q6 *1 q5 q1 ry/by# (note) in progress q7# toggling 0 0 0 exceed time limit q7# toggling 1 n/a 0 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 20 command operations (cont'd) sector erase (cont'd) the system can determine the status of the embedded sector erase operation by the following methods: chip erase the chip erase operation is used erase all the data within the memory array. all memory cells containing a "0" will be returned to the erased state of "1". this operation requires 6 write cycles to initiate the action. the frst two cycles are "unlock" cycles, the third is a confguration cycle, the fourth and ffth are also "unlock" cycles, and the sixth cycle initiates the chip erase operation. during the chip erase operation, no other software commands will be accepted, but if a hardware reset is re - ceived or the working voltage is too low, that chip erase will be terminated. after chip erase, the chip will auto - matically return to read mode. the system can determine the status of the embedded chip erase operation by the following methods: *1: ry/by# is open drain output pin and should be connected to vcc through a high value pull-up resistor. notes: 1. the q3 status bit is the 50us time-out indicator . when q3=0, the 50us time-out counter has not yet reached zero and a new sector erase command may be issued to specify the address of another sector to be erased. when q3=1, the 50us time-out counter has expired and the sector erase operation has already begun. erase suspend is the only valid command that may be issued once the embedded erase operation is underway. 2. r y/by# is open drain output pin and should be connected to vcc through a high value pull-up resistor. 3. when an attempt is made to erase only protected sector (s), the erase operation will abort thus preventing any data changes in the protected sector (s). q7 will output "0" and q6 will toggle briefy (100us or less) before aborting and returning the device to read mode. if unprotected sectors are also specifed, however, they will be erased normally and the protected sector (s) will remain unchanged. 4. q2 is a localized indicator showing a specifed sector is undergoing erase operation or not. q2 toggles when user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode). status q7 q6 q5 q3 *1 q2 ry/by# *2 time-out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 exceeded time limit 0 toggling 1 1 toggling 0 status q7 q6 q5 q2 ry/by# *1 in progress 0 toggling 0 toggling 0 exceed time limit 0 toggling 1 toggling 0 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 21 after beginning a sector erase operation, erase suspend is the only valid command that may be issued. if sys - tem issues an erase suspend command during the 50us time-out period following a sector erase command, the time-out period will terminate immediately and the device will enter erase-suspended read mode. if the system issues an erase suspend command after the sector erase operation has already begun, the device will not enter erase-suspended read mode until 20us time has elapsed. the system can determine if the device has entered the erase-suspended read mode through q6, q7, and ry/by#. after the device has entered erase-suspended read mode, the system can read or program any sector (s) ex - cept those being erased by the suspended erase operation. reading any sector being erased or programmed will return the contents of the status register. whenever a suspend command is issued, user must issue a re - sume command and check q6 toggle bit status, before issue another erase command. the system can use the status register bits shown in the following table to determine the current state of the device: command operations (cont'd) erase suspend/resume when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. sector erase resume the sector erase resume command is valid only when the device is in erase-suspended read mode. after erase resumes, the user can issue another ease suspend command, but there should be a 400us interval be - tween ease resume and the next erase suspend command. status q7 q6 q5 q3 q2 q1 ry/by# erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle n/a 1 erase suspend read in non-erase suspended sector data data data data data data 1 erase suspend program in non-erase suspended sector q7# toggle 0 n/a n/a n/a 0 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 22 command operations (cont'd) program suspend/resume when the device has program/erase suspended, user can execute read array, auto-select, read cfi, read secu - rity silicon. program resume the program resume command is valid only when the device is in program-suspended mode. after program resumes, the user can issue another program suspend command, but there should be a 5us interval between program resume and the next program suspend command. status q7 q6 q5 q3 q2 q1 ry/by# program suspend read in program suspended sector invalid 1 program suspend read in non-program suspended sector data data data data data data 1 buffer write abort q1 is the indicator of buffer write abort. when q1=1, the device will abort from buffer write and go back to read status register shown as following table: status q7 q6 q5 q3 q2 q1 ry/by# buffer write busy q7# toggle 0 n/a n/a 0 0 buffer write abort q7# toggle 0 n/a n/a 1 0 buffer write exceeded time limit q7# toggle 1 n/a n/a 0 0 after beginning a program operation, program suspend is the only valid command that may be issued. the sys - tem can determine if the device has entered the program-suspended read mode through q6 and ry/by#. after the device has entered program-suspended mode, the system can read any sector (s) except those be - ing programmed by the suspended program operation. reading the sector being program suspended is invalid. whenever a suspend command is issued, user must issue a resume command and check q6 toggle bit status, before issue another program command. the system can use the status register bits shown in the following table to determine the current state of the device: p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 23 automatic select operations when the device is in read mode, program suspended mode, erase-suspended read mode, or cfi mode, the user can issue the automatic select command shown in table 3 (two unlock cycles followed by the automatic select command 90h) to enter automatic select mode. after entering automatic select mode, the user can query the manufacturer id, device id, security sector locked status, or sector protected status multiple times without issuing a new automatic select command. while in automatic select mode, issuing a reset command (f0h) will return the device to read mode (or ease- suspended read mode if erase-suspend was active) or program suspended read mode if program suspend was active. another way to enter automatic select mode is to use one of the bus operations shown in table 2-2. bus op- eration . after the high voltage (vhv) is removed from the a9 pin, the device will automatically return to read mode or erase-suspended read mode. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not secured silicon is locked and whether or not a sector is protected. the automatic select mode has four command cycles. the frst two are unlock cycles, and followed by a specifc command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic select mode and back to read array. the following table shows the identifcation code with corresponding address. after entering automatic select mode, no other commands are allowed except the reset command. command operations (cont'd) address data (hex) representation manufacturer id word x00 c2 byte x00 c2 device id mx29gl256f word x01/0e/0f 227e/2222/2201 byte x02/1c/1e 7e/22/01 secured silicon word x03 99/19 (h) factory locked/unlocked 89/09 (l) byte x06 99/19 (h) factory locked/unlocked 89/09 (l) sector protect verify word (sector address) x 02 00/01 unprotected/protected byte (sector address) x 04 00/01 unprotected/protected p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 24 read manufacturer id or device id the manufacturer id (identifcation) is a unique hexadecimal number assigned to each manufacturer by the je - dec committee. each company has its own manufacturer id, which is different from the id of all other compa - nies. the number assigned to macronix is c2h. after entering automatic select mode, performing a read operation with a1 & a0 held low will cause the device to output the manufacturer id on the data i/o (q7 to q0) pins. reset in the following situations, executing reset command will reset device back to read mode: ? among erase command se quence (before the full command set is completed) ? sector erase time-out perio d ? erase fail (while q5 is high ) ? among program command sequence (before the full command set is completed, erase-suspended program included) ? program fail (while q5 is h igh, and erase-suspended program fail is included) ? auto-select mode ? cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in auto-select mode or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig - nore reset command. command operations (cont'd) p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 25 start q1=0 q2=0 password protection mode to choose protection mode set lock register bit (q1/q2) spb lock bit unlocked all spbs are changeable solid write protect bit (spb) spb=0 sector protect spb=1 sector unprotect temporary unprotect spb bit (uspb) uspb=0 spb bit is disabled uspb=1 spb bit is enabled uspb 0 uspb 1 uspb 2 : : uspb n-1 uspb n spb 0 spb 1 spb 2 : : spb n-1 spb n sa 0 sa 1 sa 2 : : sa n-1 sa n dpb 0 dpb 1 dpb 2 : : dpb n-1 dpb n spb lock bit locked all spbs can not changeable solid protection mode set 64 bit password sector array dynamic write protect bit (dpb) dpb=0 sector protect dpb=1 sector unprotect set spb lock bit spblk = 0 spblk = 1 advanced sector protection/un-protection there are two ways to implement software advanced sector protection on this device: password method or solid methods. through these two protection methods, user can disable or enable the programming or erasing operation to any individual sector or the whole chip. the fgure below helps to describe an overview of these methods. the device is default to the solid mode. all sectors are default as unprotected when shipped from factory. the detailed algorithm of advance sector protection is shown as follows: figure 1. advance sector protection/unprotection spb program algorithm p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 26 start pass exit lock register command done yes yes no q5 = 1 no write data aah, address 555h lock register command set entry write data 55h, address 2aah write data 40h, address 555h write data a0h, address don?t care write program data, address don?t care data # polling algorithm fail reset command lock register data program 1. lock register user can choose the sector protecting method via setting lock register bits as q1 and q2. lock register is a 16-bit one-time programmable register. once programming either q1 or q2, they will be locked in that mode and the others will be disabled permanently. q1 and q2 can not be programmed at the same time, otherwise the device will abort the operation. if users select password protection mode, the password setting is required. users can set password by issuing password program command. lock register bits q15-q3 q2 q1 q0 don't care password protection mode lock bit solid protection mode lock bit secured silicon sector protection bit please refer to the command for lock register command set about how to read and program the lock register bits. figure 2. lock register program algorithm p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 27 2. solid protection mode 2.1 solid write protection bits (spb) the solid write protection bits (spb) are nonvolatile bit with the same endurances as the flash memory. each spb is assigned to each sector individually. the spb is preprogrammed, and verified prior to erasure are managed by the device, so system monitoring is not necessary. when spb is set to 0, the associated sector may be protected, preventing any program or erase operation on this sector. whether the sector is protected depends also upon the value of the uspb, as described elsewhere. the spb bits are set individually by spb program command. however, it cannot be cleared individually. issuing the all spb erase command will erase all spb in the same time. during spb programming period, the read and write operations are disabled for normal sector until exiting this mode. to unprotect a protected sector, the spb lock bit must be cleared frst by using a hardware reset or a power-up cycle. after the spb lock bit is cleared, the spb status can be changed to the desired settings. to lock the solid protection bits after the modifcation has fnished, the spb lock bit must be set once again. to verify the state of the spb for a given sector, issuing a spb status read command to the device is required. refer to the fow chart for details in figure 3. 2.2 dynamic write protection bits (dpb) the dynamic protection features a volatile type protection to each individual sector. it can protect sectors from being unintentionally changed, and is easy to disable. all dynamic write protection bit (dpb) can be modifed individually. dpbs protect the unprotected sectors with their spbs cleared. to modify the dpb status by issuing the dpb set (programmed to 0) or dpb clear (erased to 1) commands, and place each sector in the protected or unprotected state seperately. after the dpb clear command is issued (erased to 1), the sector may be modifed depending on the spb state of that sector . the dpbs are default to be erased to 1 when frst shipped from factory . p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 28 figure 3. spb program algorithm q6 toggle ? q6 toggle ? q5 = 1 ? no no yes no no spb command set entry program spb read q7~q0 twice read q7~q0 twice read q7~q0 twice yes yes yes wait 500 s program fail write reset cmd pass q0= '1' (erase) '0' (program) spb command set exit 1 r w h 6 3 % s u r j u d p h u d v h v w d w x v s r o o l q j r z f k d u w f k h f n 4 w r j j o h z k h q 4 v w r s w r j j o h w k h u h d g v w d w x v l v + + + i r u s u r j u d p + i r u h u d v h r w k h u z l v h w k h v w d w x v l v 3 i d l o d q g 3 h [ l w 2.3 temporary un-protect solid write protect bits (uspb) temporary un-protect solid write protect bits are volatile. they are unique for each sector and can be lqglylgxdoo prglhg 6riwzduh fdq whpsrudulo xqsurwhfw zulwh surwhfw vhfwruv ghvslwh ri 63%v surshuw zkhq dpbs are cleared. while the uspb is set (to 0), the corresponding sector's spb property is masked. notes: 1. upon power up, the uspbs are cleared (all 1). the uspbs can be set (to 0) or cleared (to 1) as often as needed. the hardware reset will reset uspb/dpb to their default values. 2. to change the protected sector status of solid write protect bit, users don't need to clear all spbs. the users can just implement software to set corresponding uspb to "0", in which the corresponding dpb status is cleared too. consequently, the original solid write protect status of protected sectors can be temporarily changed. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 29 4. password protection method the security level of password protection method is higher than the solid protection mode. the 64 bit password is requested before modifying spb lock bit status. when device is under password protection mode, the spb lock bit is set as 0, after a power-up cycle or reset command. a correct password is required for password unlock command to unlock the spb lock bit. await 2us is necessary to unlock the device after a valid password is given. after that, the spb bits are allowed to be changed. the password unlock command is issued slower than 2 s every time, to prevent hacker from trying all the 64-bit password combinations. there are a few steps to start password protection mode: (1). set a 64-bit password for verifcation before entering the password protection mode. this verifcation is only allowed in password programming. (2). set the password protection mode lock bit to0 to activate the password protection mode. once the password protection mode lock bit is programmed, the programmed q2 bit can not be erased any more and the device will remain permanently in password protection mode. the previous set 64-bit password can not be retrieved or programmed. all the commands to the password-protected address will also be disabled. all the combinations of the 64-bit password can be used as a password, and programming the password does not require special address. the password is defaulted to be all 1 when shipped from the factory. under password program command, only "0" can be programmed. in order to prevent access, the password mode locking bit must be set after the password is programmed and verifed. to set the password mode lock bit will prevent this 64-bits password to be read on the data bus. any modifcation is impossible then, and the password can not be checked anymore after the password mode lock bit is set. 3. solid protection bit lock bit the solid protection bit lock bit (spblk) is assigned to control all spb status. it is an unique and volatile. when spblk=0 (set), all spbs are locked and can not be changed. when spblk=1 (cleared), all spbs are allowed to be changed. there is no software command sequence requested to unlock this bit, unless the device is in the password protection mode. to clear the spb lock bit, just execute a hardware reset or a power-up cycle. in order to prevent modifcation, the spb lock bit must be set (spblk=0) after all spbs are set to desired status. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 30 sector protection status table protection bit status sector status dpb spb uspb clear clear clear unprotect clear clear set unprotect clear set clear protect clear set set unprotect set clear clear protect set clear set protect set set clear protect set set set protect notes: if spblk is set, spb will be unchangeable. if spblk is cleared, spb will be changeable. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 31 secured silicon sector address range standard factory locked express flash factory locked customer lockable 000000h-000007h esn esn or determined by customer determined by customer 000008h-00007fh unavailable determined by customer customer lockable: security sector not programmed or protected at the factory when the security feature is not required, the security region can act as an extra memory space. security silicon sector can also be protected by two methods. note that once the security silicon sector is pro - tected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. after the security silicon is locked and verifed, system must write exit security sector region, go through a pow - er cycle, or issue a hardware reset to return the device to read normal array mode. security sector flash memory region the security sector region is an extra otp memory space of 128 words in length. the security sector can be locked upon shipping from factory, or it can be locked by customer after shipping. customer can issue security sector factory protect verify and/or security sector protect verify to query the lock status of the device. in factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit is set to "1". in customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0". factory locked: security sector programmed and protected at the factory in a factory locked device, the security sector is permanently locked before shipping from the factory. the de - vice will have a 16-byte (8-word) esn in the security region. the esn occupies addresses 00000h to 0000fh in byte mode or 00000h to 00007h in word mode. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 32 table 3. command definitions wa= write address wd= write data sa= sector address n-1= word count wbl= write buffer location pwd= password pwdn=password word 0, word 1, word n id1/id2/id3: refer to table 2-2 for detailed id. comm- and read mode reset mode automatic select security sector region exit security sector silicon id device id factory protect verify sector protect verify word byte word byte word byte word byte word byte word byte 1st bus cycle addr addr xxx 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa data data f0 aa aa aa aa aa aa aa aa aa aa aa aa 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa data 90 90 90 90 90 90 90 90 88 88 90 90 4th bus cycle addr x00 x00 x01 x02 x03 x06 (sector) x02 (sector) x04 xxx xxx data c2h c2h id1 id1 99/19(h) 89/09(l) 00/01 00/01 00 00 5th bus cycle addr x0e x1c data id2 id2 6th bus cycle addr x0f x1e data id3 id3 comm- and program write to buffer program write to buffer program abort reset write to buffer program confrm chip erase sector erase cfi read program/ erase suspend program/ erase resume word byte word byte word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr 555 aaa 555 aaa 555 aaa sa sa 555 aaa 555 aaa 55 aa xxx xxx xxx xxx data aa aa aa aa aa aa 29 29 aa aa aa aa 98 98 b0 b0 30 30 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa sa sa 555 aaa 555 aaa 555 aaa data a0 a0 25 25 f0 f0 80 80 80 80 4th bus cycle addr addr addr sa sa 555 aaa 555 aaa data data data n-1 n-1 aa aa aa aa 5th bus cycle addr wa wa 2aa 555 2aa 555 data wd wd 55 55 55 55 6th bus cycle addr wbl wbl 555 aaa sec- tor sec- tor data wd wd 10 10 30 30 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 33 command deep power down password protection enter exit password command set entry password program password read password unlock password command set exit word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr 555 aaa xxx xxx 555 aaa xxx xxx x00 x00 00 00 xxx xxx data aa aa ab ab aa aa a0 a0 pwd0 pwd0 25 25 90 90 2nd bus cycle addr 2aa 555 2aa 555 pwa pwa x01 x01 00 00 xxx xxx data 55 55 55 55 pwd pwd pwd1 pwd1 03 03 00 00 3rd bus cycle addr xxx xxx 555 aaa x02 x02 x00 x00 data b9 b9 60 60 pwd2 pwd2 pwd0 pwd0 4th bus cycle addr x03 x03 x01 x01 data pwd3 pwd3 pwd1 pwd1 5th bus cycle addr x04 x02 x02 data pwd4 pwd2 pwd2 6th bus cycle addr x05 x03 x03 data pwd5 pwd3 pwd3 7th bus cycle addr x06 00 x04 data pwd6 29 pwd4 8th bus cycle addr x07 x05 data pwd7 pwd5 9th bus cycle addr x06 data pwd6 10th bus cycle addr x07 data pwd7 11th bus cycle addr 00 data 29 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 34 command lock register global non-volatile lock register command set entry program read lock register command set exit spb command set entry spb program all spb erase spb status read word byte word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr 555 aaa xxx xxx xxx xxx xxx xxx 555 aaa xxx xxx xxx xxx sa sa data aa aa a0 a0 data data 90 90 aa aa a0 a0 80 80 00/01 00/01 2nd bus cycle addr 2aa 555 xxx xxx xxx xxx 2aa 555 sa sa 00 00 data 55 55 data data 00 00 55 55 00 00 30 30 3rd bus cycle addr 555 aaa 555 aaa data 40 40 c0 c0 4th bus cycle addr data 5th bus cycle addr data command global non- volatile global volatile freeze volatile spb command set exit spb lock command set entry spb lock set spb lock status read spb lock command set exit dpb command set entry dpb set dpb clear word byte word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr xxx xxx 555 aaa xxx xxx xxx xxx xxx xxx 555 aaa xxx xxx xxx xxx data 90 90 aa aa a0 a0 00/01 00/01 90 90 aa aa a0 a0 a0 a0 2nd bus cycle addr xxx xxx 2aa 555 xxx xxx xxx xxx 2aa 555 sa sa sa sa data 00 00 55 55 00 00 00 00 55 55 00 00 01 01 3rd bus cycle addr 555 aaa 555 aaa data 50 50 e0 e0 4th bus cycle addr data 5th bus cycle addr data command volatile dpb status read dpb command set exit word byte word byte 1st bus cycle addr sa sa xxx xxx data 00/01 00/01 90 90 2nd bus cycle addr xxx xxx data 00 00 3rd bus cycle addr data 4th bus cycle addr data 5th bus cycle addr data notes: * it is not recommended to adopt any other code not in the command defnition table which will potentially enter the hidden mode. * for the spb lock and dpb status read "00" means lock (protect), "01" means unlock (unprotect). p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 35 table 4-1. cfi mode: identifcation data values (note 1) ooydoxhvlqwkhvhwdeohvduhlqkhdghflpdo table 4-2. cfi mode: system interface data values common flash memory interface (cfi) mode query command and command flash memory interface (cfi) mode the device features cfi mode. host system can retrieve the operating characteristics, structure and vendor- vshflhg lqirupdwlrq vxfk dv lghqwlilq lqirupdwlrq phpru vl]h ewhzrug frqxudwlrq rshudwlq yrowdhv and timing information of this device by cfi mode. if the system writes the cfi query command "98h", to ad - dress "55h"/"aah" (depending on word/byte mode), the device will enter the cfi query mode, any time the de - vice is ready to read array data. the system can read cfi information at the addresses given in table 4. 2qfh xvhu hqwhuv ), txhu prgh xvhu fdq lvvxh uhvhw frppdqg wr h[lw ), prgh dqg uhwxuq wr uhdg duud prgh7kh),xqxvhgduhdlvuhvhuyhge0dfurql[ description address (h) (word mode) address (h) (byte mode) data (h) vcc supply minimum program/erase voltage 1b 36 0027 9ffvxssopd[lpxpsurudphudvhyrowdh 1c 38 0036 vpp supply minimum program/erase voltage 1d 3a 0000 933vxssopd[lpxpsurudphudvhyrowdh 1e 3c 0000 typical timeout per single word/byte write, 2 n us 1f 3e 0003 7slfdowlphrxwirupd[lpxpvl]hexiihuzulwh n us (00h, not support) 20 40 0006 typical timeout per individual block erase, 2 n ms 21 42 0009 typical timeout for full chip erase, 2 n ms (00h, not support) 22 44 0013 0d[lpxpwlphrxwiruzrugewhzulwh n times typical 23 46 0003 0d[lpxpwlphrxwiruexiihuzulwh n times typical 24 48 0005 0d[lpxpwlphrxwshulqglylgxdoeorfnhudvh n times typical 25 4a 0003 0d[lpxpwlphrxwirufklshudvh n times typical (00h, not support) 26 4c 0002 description address (h) (word mode) address (h) (byte mode) data (h) query-unique ascii string "qry" 10 20 0051 11 22 0052 12 24 0059 primary vendor command set and control interface id code 13 26 0002 14 28 0000 gguhvvirusulpdudorulwkph[whqghgtxhuwdeoh 15 2a 0040 16 2c 0000 alternate vendor command set and control interface id code 17 2e 0000 18 30 0000 gguhvvirudowhuqdwhdorulwkph[whqghgtxhuwdeoh 19 32 0000 1a 34 0000 note 1. query data are always presented on the lowest data output q7~q0 only, q8~q15 are "0". p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 36 table 4-3. cfi mode: device geometry data values description address (h) (word mode) address (h) (byte mode) data (h) device size = 2 n in number of bytes 27 4e 0019 flash device interface description (02=asynchronous x8/x16) 28 50 0002 29 52 0000 maximum number of bytes in buffer write = 2 n (00h, not support) 2a 54 0006 2b 56 0000 number of erase regions within device (01h:uniform, 02h:boot) 2c 58 0001 index for erase bank area 1: [2e,2d] = # of same-size sectors in region 1-1 [30, 2f] = sector size in multiples of 256k-bytes 2d 5a 00ff 2e 5c 0000 2f 5e 0000 30 60 0002 index for erase bank area 2 31 62 0000 32 64 0000 33 66 0000 34 68 0000 index for erase bank area 3 35 6a 0000 36 6c 0000 37 6e 0000 38 70 0000 index for erase bank area 4 39 72 0000 3a 74 0000 3b 76 0000 3c 78 0000 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 37 table 4-4. cfi mode: primary vendor-specifc extended query data values description address (h) (word mode) address (h) (byte mode) data (h) 4xhu3ulpduhwhqghgwdeohxqltxh6vwulq35 40 80 0050 41 82 0052 42 84 0049 major version number, ascii 43 86 0031 minor version number, ascii 44 88 0033 unlock recognizes address (0= recognize, 1= don't recognize) 45 8a 0014 erase suspend (2= to both read and program) 46 8c 0002 sector protect (n= # of sectors/group) 47 8e 0001 temporary sector unprotect (1=supported) 48 90 0000 sector protect/chip unprotect scheme 49 92 0008 simultaneous r/w operation (0=not supported) 4a 94 0000 burst mode (0=not supported) 4b 96 0000 page mode (0=not supported, 01 = 4 word page, 02 = 8 word page) 4c 98 0002 minimum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4d 9a 0095 0d[lpxpdffhohudwlrqvxsso qrwvxssruwhg'' for volt, [d3:d0] for 100mv 4e 9c 00a5 wp# protection 04=uniform sectors bottom wp# protect 05=uniform sectors top wp# protect 4f 9e 0004/ 0005 program suspend (0=not supported, 1=supported) 50 a0 0001 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 38 absolute maximum stress ratings operating temperature and voltage electrical characteristics storage temperature -65c to +150c voltage range vcc -0.5v to +4.0 v vi/o -0.5v to +4.0 v a9 , wp#/acc -0.5v to +10.5 v the other pins. -0.5v to vcc +0.5v output short circuit current (less than one second) 200 ma industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages full vcc range +2.7 v to 3.6 v regulated vcc range +3.0 v to 3.6 v vi/o range 1.65v to vcc notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may af fect reliability . 2. specifcations contained w ithin the following tables are subject to change. 3. durin g voltage transitions, all pins may overshoot gnd to -2.0v and vcc to +2.0v for periods up to 20ns, see below figure. maximum negative overshoot waveform maximum positive overshoot waveform gnd gnd - 2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 39 dc characteristics symbol description min. typ. max. remark iilk input leak 2.0ua iilk9 a9 leak 35ua a9=10.5v iolk output leak 1.0ua icr1 read current 5ma 15ma ce#=vil, oe#=vih, vcc=vccmax; f=1mhz 10ma 20ma ce#=vil, oe#=vih, vcc=vccmax; f=5mhz 15ma 30ma ce#=vil, oe#=vih, vcc=vccmax; f=10mhz icr2 vcc page read current 1.5ma 5ma ce#=vil, oe#=vih, vcc=vccmax; f=10mhz 3ma 10ma ce#=vil, oe#=vih, vcc=vccmax; f=33mhz iio vi/o non-active current 0.2ma 10ma icw write current 14ma 30ma ce#=vil, oe#=vih isb standby current 20ua 50ua vcc=vccmax, other pin disable isbr reset current 20ua 50ua vcc=vccmax, reset# enable, other pin disable isbs sleep mode current 20ua 50ua idpd vcc deep power down current 1ua 10ua icp1 accelerated pgm current, wp#/acc pin (word/byte) 1ma 3ma ce#=vil, oe#=vih icp2 accelerated pgm current, vcc pin, (word/byte) 7ma 14ma ce#=vil, oe#=vih vil input low voltage -0.1v 0.3xvi/o vih input high voltage 0.7xvi/o vi/o+0.3v vhv very high voltage for auto select/ accelerated program 9.5v 10.5v vol output low voltage 0.45v iol=100ua voh ouput high voltage 0.85xvi/o ioh=-100ua vlko low vcc lock-out voltage 2.1v 2.4v note: sleep mode enables the lower power when address remain stable for taa+1us. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 40 switching test circuits switching test waveforms test condition output load capacitance, cl : 1ttl gate, 30pf rise/fall times : 5ns input pulse levels :0.0 ~ vi/o in/out reference levels :0.5v i/o test points vi/o vi/o / 2 vi/o / 2 0.0v output input device under test cl 3.3v 6.2k 2.7k p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 41 ac characteristics symbol description 29gl256f (vcc=2.7v~3.6v) 29gl256f (vcc=3.0v~3.6v) unit min. typ. max. min. typ. max. ta a valid data output after address vi/o=vcc 100 90 ns vi/o=1.65 to vcc 110 110 ns tpa page access time vi/o=vcc 25 25 ns vi/o=1.65 to vcc 30 30 ns tc e valid data output after ce# low vi/o=vcc 100 90 ns vi/o=1.65 to vcc 110 110 ns to e valid data output after oe# low vi/o=vcc 25 25 ns vi/o=1.65 to vcc 30 30 ns tdf data output foating after oe# high or ce# high 20 20 ns tsrw latency between read and write operation (note) 35 35 ns to h output hold time from the earliest rising edge of address, ce#, oe# 0 0 ns trc read period time 100 90 ns twc write period time 100 90 ns tcwc command write period time 100 90 ns ta s address setup time 0 0 ns taso address setup time to oe# low during toggle bit polling 15 15 ns ta h address hold time 45 45 ns taht address hold time from ce# or oe# high during toggle bit polling 0 0 ns tds data setup time 30 30 ns tdh data hold time 0 0 ns tvcs vcc setup time 500 500 us tc s chip enable setup time 0 0 ns tc h chip enable hold time 0 0 ns toes output enable setup time 0 0 ns toeh output enable hold time read 0 0 ns toggle & data# polling 10 10 ns tws we# setup time 0 0 ns twh we# hold time 0 0 ns tcepw ce# pulse width 35 35 ns tcepwh ce# pulse width high 30 30 ns twp we# pulse width 35 35 ns twph we# pulse width high 30 30 ns tbusy program/erase active time by ry/by# vi/o=vcc 100 90 ns vi/o=1.65 to vcc 110 110 ns tghwl read recover time before write 0 0 ns tghel read recover time before write 0 0 ns p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 42 symbol description 29gl256f (vcc=2.7v~3.6v) 29gl256f (vcc=3.0v~3.6v) unit min. typ. max. min. typ. max. twhwh1 program operation byte 10 10 us twhwh1 program operation word 10 10 us twhwh1 acc program operation (word/byte) 10 10 us twhwh2 sector erase operation 0.5 3.5 0.5 3.5 sec tbal sector add hold time 50 50 us trdp release from deep power down mode 200 200 us note: not 100% tested. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 43 figure 4. command write operation addresses ce# oe# we# din tds tah data tdh tcs tch tcwc twph twp toes tas vih vil vih vil vih vil vih vil vih vil va va: valid address write command operation p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 44 read/reset operation figure 5. read timing waveforms addresses ce# oe# taa we# vih vil vih vil vih vil vih vil voh vol tsrw high z high z data valid toe toeh tdf tce trc outputs toh add valid p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 45 figure 6. reset# timing waveform trh trb1 trp2 trp1 tready2 tready1 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# trb2 we# reset# ac characteristics item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 200 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) to read or write max 20 us tready2 reset# pin low (not during automatic algorithms) to read or write max 500 ns p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 46 erase/program operation figure 7. automatic chip erase timing waveform twc address oe# ce# 55h 2aah 555h 10h in progress complete va va ta s ta h tghwl tc h twp tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tc s twph we# data ry/by# p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 47 figure 8. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 48 figure 9. automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h sector address n tas tah tbal tghwl tch twp tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by# 30h p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 49 figure 10. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase yes yes no data=ffh p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 50 figure 11. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 51 figure 12. automatic program timing waveforms figure 13. accelerated program timing diagram address oe# ce# a0h 555h pa pd status dout va va tas tah tghwl tch twp tds tdh twhwh1 last 2 read status cycle last 2 program command cycle tbusy trb tcs twph we# data ry/by# wp#/acc vcc 250ns 250ns vhv (9.5v ~ 10.5v) vil or vih vil or vih tvcs vcc (min) gnd p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 52 figure 14. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcepw tds tdh twhwh1 or twhwh2 tbusy tcepwh we# data ry/by# tws twh p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 53 figure 15. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last word to be programed no no p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 54 figure 16. silicon id read timing waveform ta a ta a ta a ta a tc e to e to h to h to h to h tdf data out manufacturer id device id cycle 1 device id cycle 2 device id cycle 3 vhv vih vil add a9 add ce# a1 oe# we# add a0 data out data out data out data q15-q0 vcc 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil a2 disable enable p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 55 write operation status figure 17. data# polling timing waveforms (during automatic algorithms) tdf tce tch toe toeh toh ce# oe# we# q7 q6-q0 ry/by# tbusy status data status data complement complement true valid data taa trc address va va high z high z valid data true p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 56 figure 18. status polling for word program/erase notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 may change simultaneously with q5, so even q5=1, q7 should be reverify. start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no yes yes yes read data at valid address (note 1) read data at valid address (note 1) p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 57 figure 19. status polling for write buffer program read data at last write address (note 1) start q7 = data# ? q1=1 ? only for write buffer program q7 = data# ? (note 2) fail pass write buffer abort no no no no no yes yes q5=1 ? yes yes yes read data at last write address (note 1) q7 = data# ? (note 2) read data at last write address (note 1) notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 may change simultaneously with q5, so even q5=1, q7 should be reverify. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 58 figure 20. toggle bit timing waveforms (during automatic algorithms) tdf taht taso tce tch toe toeh taa trc toh address ce# oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va va : valid address va valid data p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 59 figure 21. toggle bit algorithm notes: 1. toggle bit q7-q0 should be read twice to check if it is toggling. 2. while q5=1, the toggle bit (q6) may stop toggling. therefore, the system should be read again. start q5 = 1 ? fail pass no no no yes yes yes read data twice (note 1) read data twice (note 1, 2) q6 toggle ? q6 toggle ? p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 60 figure 22. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ac characteristics word/byte configuration (byte#) parameter description test setup all speed options unit telf/telfh ce# to byte# from l/h max. 5 ns tfqz byte# from l to output hiz max. 30 ns tfhqv byte# from h to output active min. 90 ns tfhqv telfh dout (q0-q7) dout (q0-q14) va dout (q15) ce# oe# byte# q14~q0 q15/a-1 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 61 figure 23. page read timing waveform amax:a3 (a-1),a0,a1,a2 data ce# note: ce#, oe# are enable. page size is 8 words in word mode, 16 bytes in byte mode. address are a2~a0 for word mode, a2~a-1 for byte mode. valid add data 1 data 2 data 3 1'st add 2'nd add tpa ta a 3'rd add tpa oe# tc e to e p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 62 figure 24. deep power down mode waveform ceb web add data xx b9 2aa 55 tdp xx (don' t care) ab s tan db y m ode aa 55 dee p po we r down m od e trdp s tan db y m ode item typ max web high to release from deep power down mode trdp 100us 200us web high to deep power down mode tdp 10us 20us ac characteristics p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 63 figure 25. write buffer program flowchart write cmd: data=aah, addr=555h write cmd: data=55h, addr=2aah write cmd: data=25h, addr=sa sa: sector address of to be programmed page write cmd: data=pwc, addr=sa pwc: program word count write cmd: data=pgm_data, addr=pgm_addr pwc =0? write cmd: data=29h, addr=sa polling status yes pass no no write buffer abort write reset cmd to return to read mode pwc=pwc-1 no fail yes want to abort ? yes no no yes return to read mode wr ite abort reset cmd to return to read mode wr ite a different sector address to ca use abort yes p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 64 recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power- up (e.g. vcc and ce# ramp up simultaneously). if the timing in the fgure is ignored, the device may not operate correctly. figure a. ac timing at device power-up vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vi/o vi/o(min) gnd vih vil vih vil vih vil vih vil vih vil voh high z vol wp#/acc valid ouput valid address tvcs tvr tvios tr toe tf tr symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v tvcs vcc setup time 500 us tvios vi/o setup time 500 us notes: 1. vi/o 66 ordering information part no. access time (ns) package remark mx29gl256fhxfi-90q * 90 64 lfbga vi/o=vcc mx29gl256flxfi-90q * 90 64 lfbga vi/o=vcc mx29gl256fht2i-90q * 90 56 pin tsop vi/o=vcc mx29gl256flt2i-90q * 90 56 pin tsop vi/o=vcc mx29gl256fhxgi-90q * 90 56 fbga vi/o=vcc mx29gl256flxgi-90q * 90 56 fbga vi/o=vcc mx29gl256fuxfi-11g 110 64 lfbga vi/o=1.65 to vcc mx29gl256fdxfi-11g 110 64 lfbga vi/o=1.65 to vcc mx29gl256fut2i-11g 110 56 pin tsop vi/o=1.65 to vcc mx29gl256fdt2i-11g 110 56 pin tsop vi/o=1.65 to vcc mx29gl256fuxgi-11g 110 56 fbga vi/o=1.65 to vcc mx29gl256fdxgi-11g 110 56 fbga vi/o=1.65 to vcc notes : * 90q covers 2.7v~3.6v for 100ns and 3.0v~3.6v for 90ns. p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 67 part name description mx 29 gl 90 f h t2 i q option: q: rohs compliant & halogen-free with restricted vcc: 3.0v~3.6v (note 1) g: rohs compliant & halogen-free with vcc: 2.7v~3.6v speed: 90: 90ns 11: 110ns temperature range: i: industrial (-40 c to 85 c) package: product type: (wp#=vil) h: vi/o=vcc=2.7 to 3.6v, highest address sector protected l: vi/o=vcc=2.7 to 3.6v, lowest address sector protected u: vi/o=1.65 to vcc, vcc=2.7 to 3.6v, highest address sector protected d: vi/o=1.65 to vcc, vcc=2.7 to 3.6v, lowest address sector protected revision: f density & mode: 256: 256mb x8/x16 architecture gl: 3v page mode type: device: 29:flash 256 t2: 56-tsop xf: lfbga (11mm x 13mm x 1.4mm, 0.6 ball size, 1.0 ball-pitch) xg: fbga (7mm x 9mm x 1.2mm, 0.4 ball size, 0.8 ball-pitch) note: 90q covers 2.7v~3.6v for 100ns and 3.0v~3.6v for 90ns p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 68 package information p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 69 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 70 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 71 revision history revision no. description page date 0.01 1. modifed chip erase time p63 aug/02/2010 2. modifed sector erase time p5,42,63 3. modifed notes 3 p63 4. modifed part no. and ordering information p67,68 0.02 1. removed mx29gl256f u/d function p5,57 oct/18/2010 2. modifed low vcc lock-out voltage p39 3. removed w ord/byte confguration (byte#) & p60 figure 19. byte# timing waveform for read operations 4. changed title from "advanced information" to "preliiminary" p5 5. removed 70-ssop package information p5,64,65 6. modife sector protection status table p30 1.0 1. removed the title "preliiminary" p5 mar/18/201 1 2. modifed figure 10 and figure 14 p51,55 3. modifed cin2 of pin cap acitance p63 4. added mx29gl256f u/d function p5,65,66 5. modifed erase/program cycle p5,63 1.1 1. modifed figure 16. status polling for write buffer program for p15,57 jul/04/201 1 abort function 2. modifed total write buffer time from 200us(typ.) to 120us(typ.) p63 3. modifed standby current & sleep mode current p5,39 1.2 1. added 56-ball fbga package information p5,7,64,65, oct/28/201 1 p68 1.3 1. added mx29gl256f u/d pin confguration and p7,64 jan/12/2012 ordering information for 56-fbga 2. modifed figure 11. ce# controlled write timing waveform p52 1.4 1. added "note 1. query data are always presented on the lowest p35 aug/12/2013 data output q7~q0 only , q8~q15 are "0". 2. added word/byte confguration (byte#) & p60 figure 19. byte# timing waveform for read operations 3. modifed figure 23. page read timing waveform p61 4. added vi/o setup time p64 5. added max. total write buffer time (480us) p65 6. advanced sector protection/un-protection description updated p25~30 1.5 1. updated parameters for dc characteristics. p5,39 oct/30/2013 2. updated erase and programming perform ance. p5,42,65 3. content correction p25~30 p/n:pm1544 rev. 1.5, oct. 30, 2013 mx29gl256f 72 mx29gl256f macronix international co., ltd. reserves the right to change product and specifcations without notice. ecept or custoied products which have een epress identifed in the appicae agreeent, macronis products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, shuvrqdolqmxuruvhyhuhsurshuwgdpdhv,qwkhhyhqw0dfurql[surgxfwvduhxvhglqfrqwudglfwhgwrwkhlu wduhwxvdhderyhwkhexhuvkdoowdnhdqdqgdoodfwlrqvwrhqvxuhvdlg0dfurql[vsurgxfwtxdolhgirulwv dfwxdoxvhlqdffrugdqfhzlwkwkhdssolfdeohodzvdqguhxodwlrqvdqg0dfurql[dvzhoodvlwvvxssolhuvdqgru distributors shall be released from any and all liability arisen therefrom. rsulkw 0dfurql[ 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